1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device mounted on a system LSI driven with a low power supply voltage.
2. Description of the Background Art
In order to process data with high speed and low power consumption, in a field of data processing, a circuit device referred to as a system LSI (large-scale integrated circuit) has been in widespread use, in which a logic such as an analogue processing circuit, for example, an A/D conversion circuit, and a memory device such as a DRAM (dynamic random access memory) are integrated on the same semiconductor chip.
In the system LSI, recently, lower voltage has been demanded, and accordingly, lower power supply voltage has been required also in the aforementioned embedded DRAM.
On the other hand, in the embedded DRAM, the use of a lower power supply voltage is not achieved simultaneously with a required high-speed performance due to a sensing operation of a sense amplifier.
The sense amplifier refers to a differential amplifier connected to a bit line pair having memory cells connected. The sense amplifier uses a reference voltage to amplify a weak signal that appears on one of the bit line pair from a selected memory cell by a differential voltage between the line pair, thus performing polarity discrimination.
Here, a method of generating the reference voltage is different, depending on a scheme of precharging a bit line. That is, the scheme of precharging the bit line includes a Vcc precharge scheme and a ½ Vcc precharge scheme.
In the Vcc precharge scheme, a precharge voltage of the bit line is set to power supply voltage Vcc which is a maximum voltage that a data line can have. In such a scheme, a reference voltage generating circuit is necessary to generate an intermediate value between two signal voltages. The reason is as follows. When a memory cell storing Vcc voltage is read, there is no potential difference between a storage node of the cell and the bit line. Therefore, there is no voltage change in the bit line, and thus no voltage difference appears between the line pair.
On the other hand, in the ½ Vcc precharge scheme, a precharge voltage of the bit line is set to an intermediate value between power supply voltage Vcc, which is a maximum of the bit line, and a ground potential Vss, which is a minimum of the same. Here, since a signal voltage corresponding to binary information appears relative to ½ Vcc, the reference voltage generating circuit is not needed, and the reference voltage is equal to ½ Vcc.
The Vcc precharge scheme has mainly been used in the sense amplifier in a conventional DRAM, however, a shift toward the ½ Vcc precharge scheme has been seen. This is because the ½ Vcc precharge scheme has satisfactory noise resistance, low power characteristics, a wide voltage margin, and the like.
In the ½ Vcc precharge scheme, however, a problem has been found in a high-speed operation, as the lower power supply voltage is demanded.
In the ½ Vcc precharge scheme, for a transistor within the sense amplifier, an operation point at the beginning of sensing attains a relation of Vgs=½Vcc+|slight potential difference that appeared at the bit line pair| when Vsb=½ Vcc. Therefore, when Vcc is lowered, Vgs approaches a threshold voltage of the transistor. Accordingly, the transistor cannot sufficiently be turned on, and enters what is called a “dead band of sensing” in the sense amplifier. Thus, the sense amplifier cannot perform sensing operation with high speed, and it is difficult to shorten a cycle time.
In the current embedded DRAM in which a lower voltage is required, priority is given to the high-speed operation of the sense amplifier, and the Vcc precharge scheme has been adopted again.
The reason is as follows. In the Vcc precharge scheme, for the transistor in the sense amplifier, the operation at the beginning of sensing is eased so as to attain a relation of Vgs=Vcc+|slight potential difference that appeared at the bit line pair|. Therefore, if Vcc is lowered, the transistor does not enter the dead band of sensing described above, and the high-speed sensing operation can be performed.
Because of the same reason, a Vss precharge scheme in which the precharge voltage of the bit line pair is set to ground voltage Vss (=SGND) is also adopted.
Here, the Vcc precharge scheme and the Vss precharge scheme require the reference voltage generating circuit, because the precharge voltage of the bit line pair cannot be employed as the reference voltage, as described above.
Conventionally, in the Vcc and Vss precharge schemes, one method has been adopted, in which a dummy cell including a capacitor having a structure similar to a memory cell and having a capacitance half a capacitor in the capacitance of the memory cell is arranged in a memory array, and a read voltage which is an intermediate value of the binary information of the memory cell, and is output to the bit line pair when the dummy cell is selected simultaneously with the memory cell, is used as the reference voltage.
As a method of generating the reference voltage, another method has been adopted, in which a dummy word line is newly disposed in the memory array, the dummy word line is connected to complementary bit lines constituting the bit line pair via a capacitor, and the dummy word line is driven to a selected state when the memory cell is selected based on an external address, to generate the reference voltage at the intermediate value of the binary information of the memory cell, accurately at a potential of the complementary bit lines by capacitive coupling. This is proposed, for example, in Japanese Patent Laying-Open No. 63-282994, and in a reference, “A 1 Mb CMOS DRAM with Fast Page and Static Column Modes,” Shozo Saito, et al., IEEE International Solid State Circuits Conference Digest of Technical Papers, pp.252-253, Feb. 15, 1985.
In the former method of arranging the dummy cell within the memory array, however, it is difficult, in the viewpoint of process, to form the dummy cell having a capacitance half the cell capacitance in a portion of the memory cell array, as the memory cell has adopted a three-dimensionally structured capacitor such as a stacked capacitor and a trench capacitor, to achieve smaller size. That is, it is difficult to generate the reference voltage with sufficient accuracy.
In addition, the latter method of generating the reference voltage in the bit line by capacitive coupling of the capacitor connected between the dummy word line and the bit line has following defects. That is, the potential that appears at the bit line is small because the capacitance of the capacitor is small, and a sufficient sense margin cannot be secured. Moreover, in the highly integrated memory array, the capacitance of the capacitor connected in parallel with the dummy word line is increased, and a time difference is caused in generating a potential that appears at each bit line when the dummy word line is activated. Further, characteristics are varied among capacitors due to a manufacturing process.
As described above, in the conventional ½ Vcc precharge scheme and the Vcc (or Vss) precharge scheme, a high-speed and normal sensing operation in the sense amplifier cannot be performed under the low power supply voltage. That is, in such schemes, it is difficult to adopt further lower voltage.